Evaluation for anomalous stress-induced leakage current of gate SiO 2 films using array test pattern

Yuki Kumagai, Akinobu Teramoto, Takuya Inatsuka, Rihito Kuroda, Tomoyuki Suwa, Shigetoshi Sugawa, Tadahiro Ohmi

Research output: Contribution to journalArticlepeer-review

7 Citations (Scopus)

Abstract

Using the array test pattern, gate current through the tunnel oxide on the order of 10-16A can be measured for about 1000000 transistors within 4 min. Because this test pattern can be fabricated by simple processes and its peripheral circuits are simple structures, the tunnel dielectric formation method and condition can be changed drastically. It was found that anomalous stress-induced leakage current (SILC) appears or disappears by applying electrical stress, and it is annealed out during a relatively high temperature measurement at 60 °C. Random telegraph signal in SILC can be observed in some transistors. These are very similar phenomena observed in Flash memory cells. We consider that, using this test pattern for the development of tunnel oxide, we can clarify the origin of anomalous SILC and promote the downscaling of tunnel oxide thickness.

Original languageEnglish
Article number5985516
Pages (from-to)3307-3313
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume58
Issue number10
DOIs
Publication statusPublished - 2011 Oct

Keywords

  • Electrical stress
  • Flash memory
  • gate leakage current
  • low current detection
  • test pattern
  • tunnel oxide

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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