Advances in CMOS technology has allowed a continuous increase in microprocessor performance by improving clock speed and by integrating more transistors on a single chip. However, as the level of Integration increases, physical constraints related to on-chip wire delays become dominant. To reduce the influence of these delays, a future microprocessor chip will need be partitioned into a collection of smaller processing units, each one with its own functionality and with reduced length of wires. Microprocessors containing large structures will not be compatible with future technologies. In this paper, we describe the wire delay problem and make simplified estimations to evaluate the influence of wire delays in the clock speed of future microprocessors, for several chip-partitioning configurations. We then provide performance estimations for these configurations, considering a range of applications with different degrees of parallelism. Our results show that partitioned chips could achieve better performance not only with parallel but also with sequential applications. In addition, our results also show that, for most applications, there is an optimal chip-partitioning configuration.