TY - GEN
T1 - Epitaxial graphene top-gate FETs on silicon substrates
AU - Kang, Hyun Chul
AU - Karasawa, Hiromi
AU - Miyamoto, Yu
AU - Handa, Hiroyuki
AU - Fukidome, Hirokazu
AU - Suemitsu, Tetsuya
AU - Suemitsu, Maki
AU - Otsuji, Taiichi
N1 - Funding Information:
The Project is supported by JST-CREST. The device process in this work was carried out at the Laboratory for Nanoelectronics and Spintronics in the Research Institute of Electrical Communication, Tohoku University.
PY - 2009
Y1 - 2009
UR - http://www.scopus.com/inward/record.url?scp=77949388862&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77949388862&partnerID=8YFLogxK
U2 - 10.1109/ISDRS.2009.5378157
DO - 10.1109/ISDRS.2009.5378157
M3 - Conference contribution
AN - SCOPUS:77949388862
SN - 9781424460304
T3 - 2009 International Semiconductor Device Research Symposium, ISDRS '09
BT - 2009 International Semiconductor Device Research Symposium, ISDRS '09
T2 - 2009 International Semiconductor Device Research Symposium, ISDRS '09
Y2 - 9 December 2009 through 11 December 2009
ER -