TY - GEN
T1 - Enhancing SRAM performance by advanced FinFET device and circuit technology collaboration for 14nm node and beyond
AU - Endo, Kazuhiko
AU - O'Uchi, Shin Ichi
AU - Matsukawa, Takashi
AU - Liu, Yongxun
AU - Sakamoto, Kunihiro
AU - Mizubayashi, Wataru
AU - Migita, Shinji
AU - Morita, Yukinori
AU - Ota, Hiroyuki
AU - Suzuki, Eiichi
AU - Masahara, Meishoku
PY - 2013/9/17
Y1 - 2013/9/17
N2 - This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVμm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing the independent-double-gate (IDG) FinFET.
AB - This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVμm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing the independent-double-gate (IDG) FinFET.
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M3 - Conference contribution
AN - SCOPUS:84883799652
SN - 9784863483484
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - T214-T215
BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013
Y2 - 12 June 2013 through 14 June 2013
ER -