Enhancing SRAM performance by advanced FinFET device and circuit technology collaboration for 14nm node and beyond

Kazuhiko Endo, Shin Ichi O'Uchi, Takashi Matsukawa, Yongxun Liu, Kunihiro Sakamoto, Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Eiichi Suzuki, Meishoku Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

This paper presents a high performance and highly reliable SRAM realized by collaboration between advanced FinFET device and circuit technology. As for the device technology, the amorphous metal gate FinFET with the record smallest AVt value (=1.34 mVμm) are demonstrated. As for the circuit technology, it is demonstrated that both reliability and performance of SRAM are dramatically enhanced by introducing the independent-double-gate (IDG) FinFET.

Original languageEnglish
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesT214-T215
Publication statusPublished - 2013 Sep 17
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: 2013 Jun 122013 Jun 14

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period13/6/1213/6/14

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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