TY - GEN
T1 - Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs
AU - Mondigo, Antoniette
AU - Sano, Kentaro
AU - Takizawa, Hiroyuki
N1 - Funding Information:
ACKNOWLEDGMENT This research was partially supported by Grant-in-Aid for Scientific Research (B) No.17H01706 from MEXT, Japan. The authors thank the support of Intel university program.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/12
Y1 - 2018/12
N2 - Stream computing is an area where FPGAs can be suitably utilized to meet high performance and high scalability demands. To achieve these, a deep computing pipeline is implemented on multiple FPGAs where stream computing is performed. This paper presents an approach to utilize two masters in a 1D ring network of multiple FPGAs for a single stream computation. Each master FPGA will be reading and writing to their respective DDR3 memories alternately, while streaming through the slave FPGAs. This is done in order to synchronize the computational results on physically separate memory units. Due to this, the aggregate memory bandwidth is doubled, which suggests enhanced performance. The introduction of this streaming concept lays the groundwork towards full utilization of memories in all the FPGAs, as an identified future work.
AB - Stream computing is an area where FPGAs can be suitably utilized to meet high performance and high scalability demands. To achieve these, a deep computing pipeline is implemented on multiple FPGAs where stream computing is performed. This paper presents an approach to utilize two masters in a 1D ring network of multiple FPGAs for a single stream computation. Each master FPGA will be reading and writing to their respective DDR3 memories alternately, while streaming through the slave FPGAs. This is done in order to synchronize the computational results on physically separate memory units. Due to this, the aggregate memory bandwidth is doubled, which suggests enhanced performance. The introduction of this streaming concept lays the groundwork towards full utilization of memories in all the FPGAs, as an identified future work.
KW - 1D ring topology
KW - deep pipeline
KW - enhanced memory bandwidth
KW - high performance
KW - multiple FPGAs
KW - stream computing
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U2 - 10.1109/FPT.2018.00078
DO - 10.1109/FPT.2018.00078
M3 - Conference contribution
AN - SCOPUS:85068337204
T3 - Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018
SP - 381
EP - 383
BT - Proceedings - 2018 International Conference on Field-Programmable Technology, FPT 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th International Conference on Field-Programmable Technology, FPT 2018
Y2 - 10 December 2018 through 14 December 2018
ER -