Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Kazuhiko Endo, Yuki Ishikawa, Takashi Matsukawa, Yongxum Liu, Shin Ichi O'Uchi, Kunihiro Sakamoto, Junichi Tsukada, Hiromi Yamauchi, Meishoku Masahara

Research output: Contribution to journalArticlepeer-review

12 Citations (Scopus)

Abstract

We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO 2 thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance (R para) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS.

Original languageEnglish
Pages (from-to)13-18
Number of pages6
JournalSolid-State Electronics
Volume74
DOIs
Publication statusPublished - 2012 Aug 1
Externally publishedYes

Keywords

  • Atomic layer deposition
  • FinFET
  • Parasitic resistance
  • Sidewall spacer

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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