Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Kazuhiko Endo; Yuki Ishikawa; Takashi Matsukawa; Yongxum Liu; Shin Ichi O'Uchi; Kunihiro Sakamoto; Junichi Tsukada; Hiromi Yamauchi; Meishoku Masahara

doi:10.1016/j.sse.2012.04.005

Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition

Kazuhiko Endo, Yuki Ishikawa, Takashi Matsukawa, Yongxum Liu, Shin Ichi O'Uchi, Kunihiro Sakamoto, Junichi Tsukada, Hiromi Yamauchi, Meishoku Masahara

Research output: Contribution to journal › Article › peer-review

12 Citations (Scopus)

Abstract

We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO ₂ thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance (R _para) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS.

Original language	English
Pages (from-to)	13-18
Number of pages	6
Journal	Solid-State Electronics
Volume	74
DOIs	https://doi.org/10.1016/j.sse.2012.04.005
Publication status	Published - 2012 Aug 1
Externally published	Yes

Keywords

Atomic layer deposition
FinFET
Parasitic resistance
Sidewall spacer

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

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Enhancement of FinFET performance using 25-nm-thin sidewall spacer grown by atomic layer deposition. / Endo, Kazuhiko; Ishikawa, Yuki; Matsukawa, Takashi; Liu, Yongxum; O'Uchi, Shin Ichi; Sakamoto, Kunihiro; Tsukada, Junichi; Yamauchi, Hiromi; Masahara, Meishoku.

In: Solid-State Electronics, Vol. 74, 01.08.2012, p. 13-18.

Research output: Contribution to journal › Article › peer-review

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abstract = "We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO 2 thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance (R para) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS.",

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AU - O'Uchi, Shin Ichi

AU - Sakamoto, Kunihiro

AU - Tsukada, Junichi

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