Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

Nobuyuki Sugii; Digh Hisamoto; Katsuyoshi Washio; Natsuki Yokoyama; Shin'ichiro Kimura

Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

Nobuyuki Sugii, Digh Hisamoto, Katsuyoshi Washio, Natsuki Yokoyama, Shin'ichiro Kimura

Research output: Contribution to journal › Conference article › peer-review

Abstract

Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ∼1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (L_eff=0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

Original language	English
Pages (from-to)	737-740
Number of pages	4
Journal	Technical Digest - International Electron Devices Meeting
Publication status	Published - 2001 Dec 1
Externally published	Yes
Event	IEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States Duration: 2001 Dec 2 → 2001 Dec 5

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering
Materials Chemistry

Cite this

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title = "Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate",

abstract = "Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ∼1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff=0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.",

author = "Nobuyuki Sugii and Digh Hisamoto and Katsuyoshi Washio and Natsuki Yokoyama and Shin'ichiro Kimura",

year = "2001",

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language = "English",

pages = "737--740",

journal = "Technical Digest - International Electron Devices Meeting",

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TY - JOUR

T1 - Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

AU - Sugii, Nobuyuki

AU - Hisamoto, Digh

AU - Washio, Katsuyoshi

AU - Yokoyama, Natsuki

AU - Kimura, Shin'ichiro

PY - 2001/12/1

Y1 - 2001/12/1

N2 - Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ∼1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff=0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

AB - Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ∼1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff=0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

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M3 - Conference article

AN - SCOPUS:0035714397

SN - 0163-1918

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EP - 740

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - IEEE International Electron Devices Meeting IEDM 2001

Y2 - 2 December 2001 through 5 December 2001

ER -

Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

Abstract

ASJC Scopus subject areas

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