Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

Nobuyuki Sugii, Digh Hisamoto, Katsuyoshi Washio, Natsuki Yokoyama, Shin'ichiro Kimura

Research output: Contribution to journalConference articlepeer-review

30 Citations (Scopus)


Strained-Si n- and p-MOSFETs have been fabricated on a chemical-mechanical planarized (CMP) SiGe virtual substrate (VS). By applying CMP after growing the SiGe buffer layer, the surface roughness was considerably reduced, to 0.4 nm (rms). Large increases in mobility, of 120% and 42%, were obtained for electrons and holes, respectively, over the universal mobility at a vertical field of ∼1.5 MV/cm. Improvements in current drive of 70% and 51% were also observed for n- and p- MOSFETs (Leff=0.24 μm), respectively. These results indicate that the planarization of the SiGe VS is a critical technology for developing high-performance strained-Si CMOS.

Original languageEnglish
Pages (from-to)737-740
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 2001 Dec 1
Externally publishedYes
EventIEEE International Electron Devices Meeting IEDM 2001 - Washington, DC, United States
Duration: 2001 Dec 22001 Dec 5

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


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