Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The capacity and the energy consumption of the last-level cache (LLC) must be improved toward future microprocessors. This paper proposes an STT-RAM-based hybrid cache architecture (HCA) and its replacement policy, named the Fast Region First Used (FRFU) policy. The proposed HCA is composed of two types of STT-RAM devices with different characteristics to mitigate the disadvantages of non-volatile STT-RAM devices. The FRFU policy provides the better handling of the data blocks for the proposed HCA than the LRU policy. The evaluation results show that the proposed HCA and its policy can successfully reduce the energy consumption by 55% and improve the performance by 1% on average compared with a conventional SRAM LLC.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728163475
DOIs
Publication statusPublished - 2020 Apr
Event23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Kokubunji, Japan
Duration: 2020 Apr 152020 Apr 17

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020 - Proceedings

Conference

Conference23rd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2020
CountryJapan
CityKokubunji
Period20/4/1520/4/17

Keywords

  • STT-RAM
  • data replacement policy
  • energy consumption
  • hybrid cache architecture

ASJC Scopus subject areas

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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