Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Recently in semiconductor memories such as embedded memories (SRAM, e-DRAM), main memories (DRAM) and storage memories (NAND memory), it is becoming difficult to meet the target performance only by scaling technologies. Especially for high speed embedded memories, the large power consumption brings more serious issues due to rapid increase in memory capacity under multi core MPUs, operation speed and leakage current of scaled CMOS. Moreover, the speed gap between each memory levels in addition to that between the operation speed of MPUs and that of embedded memories and main memories have expanded year by year.

Original languageEnglish
Title of host publication2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509058051
DOIs
Publication statusPublished - 2017 Jun 7
Event2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, Taiwan, Province of China
Duration: 2017 Apr 242017 Apr 27

Publication series

Name2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Other

Other2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
CountryTaiwan, Province of China
CityHsinchu
Period17/4/2417/4/27

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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  • Cite this

    Endoh, T. (2017). Embedded nonvolatile memory with STT-MRAMs and its application for nonvolatile brain-inspired VLSIs. In 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 [7942446] (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2017.7942446