Electrical evaluation of Cu contamination behavior at the backside surface of a thinned wafer by transient capacitance measurement

Kanuku Ri, Jichoru Be, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

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11 Citations (Scopus)

Abstract

The behavior of Cu contamination at the backside surface of a thinned wafer in a three-dimensional (3D) LSI was electrically evaluated by capacitance-time (C-t) analysis. In order to electrically evaluate Cu diffusion characteristics, MOS capacitors were fabricated using the thinned wafer of 50 μm and 100 μm thickness, respectively. For an accelerated Cu diffusion test, a thin Cu layer was deposited at the back surface as a contamination source. Cu atoms were artificially diffused into the substrate by annealing at 200 °C and 300 °C for various times in nitrogen ambient. The C-t curves of a MOS capacitor formed on a 100 μm thickness substrate were degraded even after annealing at 200 °C. It means that Cu atoms diffuse into the active region and reach the Si-SiO2 interface during relatively low-temperature annealing. By increasing time and temperature, the transient time tf is more seriously decreased. The C-t curves of the MOS capacitor formed on the Si substrate of 50 μm thickness were more seriously degraded even after the initial annealing at 200 °C for 5 min. These results indicate that the Cu contamination issue becomes more severe in a thinner Si substrate.This study shows that C-t analysis is a highly promising method to electrically evaluate the influence of Cu contamination on device reliability in the 3D LSI.

Original languageEnglish
Article number025007
JournalSemiconductor Science and Technology
Volume26
Issue number2
DOIs
Publication statusPublished - 2011 Feb 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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