EFFECTS OF SURFACE STATES ON DEVICE AND INTERCONNECT ISOLATION IN GaAs MESFET AND InP MISFET INTEGRATED CIRCUITS.

H. Hasegawa, T. Kitagawa, H. Masuda, H. Yano, H. Ohno

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

Surface electrical breakdown and side-gating which cause failure of device and interconnect isolation are investigated for GaAs MESFET and InP MISFET integrated circuit structures. Differences in behavior are observed between GaAs and InP as regards to the surface conduction, surface breakdown and side-gating. These differences are shown to be related to the surface state properties of the insulator-semiconductor interface. In GaAs, high density of surface states rather than bulk trap states control the surface I-V characteristics and side-gating, causing serious premature avalanche breakdown and triggering side-gating at a low nominal field intensity of 1-3 kV/cm. InP MISFET integrated circuits are virtually free from these premature breakdown and side-gating effect under normal dark operating condition because of very low surface state density.

Original languageEnglish
Pages (from-to)227-241
Number of pages15
JournalProceedings - The Electrochemical Society
Volume86-3
Publication statusPublished - 1986
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)

Fingerprint Dive into the research topics of 'EFFECTS OF SURFACE STATES ON DEVICE AND INTERCONNECT ISOLATION IN GaAs MESFET AND InP MISFET INTEGRATED CIRCUITS.'. Together they form a unique fingerprint.

Cite this