Effects of MSHR and prefetch mechanisms on an on- chip cache of the vector architecture

Akihiro Musa, Yoshiei Sato, Takashi Soga, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

Vector supercomputers have been encountering the memory wall problem and their memory bandwidth per flop/s rate has decreased. To cover the insufficient memory bandwidth per flop/s rate, an on-chip vector cache has been proposed for the vector processors. Although vector caching is effective to increase the sustained performance to a certain degree, it still needs software and hardware supporting mechanisms to extract its potential. To this end, we propose miss status handling registers (MSHR) and a prefetch mechanism. This paper evaluates the performance of the vector cache with the MSHR and the prefetch mechanism on the vector supercomputer across three leading scientific applications. The MSHR is an effective mechanism for handling subsequent vector loads of the same data, which frequently appear in different schemes. The experimental results indicate that the MSHR can improve the computational performance of scientific applications by 1.45 ×. Moreover, we examine the performance of the prefetch mechanism on the vector cache. The prefetch mechanism increases the computational performance by 1.6×. Accordingly, the MSHR and the prefetching mechanism are very effective optimization options for vector caching of future vector supercomputers even if the vector supercomputers cannot maintain the current memory bandwidth per flop/s rate.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008
Pages335-342
Number of pages8
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008 - Sydney, NSW, Australia
Duration: 2008 Dec 102008 Dec 12

Publication series

NameProceedings of the 2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008

Other

Other2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008
CountryAustralia
CitySydney, NSW
Period08/12/1008/12/12

ASJC Scopus subject areas

  • Computer Science Applications
  • Software

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    Musa, A., Sato, Y., Soga, T., Egawa, R., Takizawa, H., Okabe, K., & Kobayashi, H. (2008). Effects of MSHR and prefetch mechanisms on an on- chip cache of the vector architecture. In Proceedings of the 2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008 (pp. 335-342). [4725165] (Proceedings of the 2008 International Symposium on Parallel and Distributed Processing with Applications, ISPA 2008). https://doi.org/10.1109/ISPA.2008.100