Effects of metal layer insertion on EOT scaling in TiN/Metal/La 2O3/Si High-k gate stacks

P. Ahmet, D. Kitayama, T. Kaneda, T. Suzuki, T. Koyanagi, M. Kouda, M. Mamatrishat, T. Kawanago, K. Kakushima, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Effects of a thin metal layer (W, Ta, or Mo) inserted at the interface between La2O3 high-k gate dielectric and TiN gate metal were studied. It was found that the inserted metal layer plays crucial role in determining the electrical characteristics of the TiN/Metal/La2O 3/Si gate stack. Our results show that EOT can be scaled to 0.5nm and below by inserting a W layer with optimum thickness at the interface between La2O3 high-k gate dielectric and the TiN gate metal.

Original languageEnglish
Title of host publicationSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications
Pages305-308
Number of pages4
Edition2
DOIs
Publication statusPublished - 2011
Externally publishedYes
EventSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications - 219th ECS Meeting - Montreal, QC, Canada
Duration: 2011 May 22011 May 4

Publication series

NameECS Transactions
Number2
Volume35
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications - 219th ECS Meeting
CountryCanada
CityMontreal, QC
Period11/5/211/5/4

ASJC Scopus subject areas

  • Engineering(all)

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