Effects of a thin metal layer (W, Ta, or Mo) inserted at the interface between La2O3 high-k gate dielectric and TiN gate metal were studied. It was found that the inserted metal layer plays crucial role in determining the electrical characteristics of the TiN/Metal/La2O 3/Si gate stack. Our results show that EOT can be scaled to 0.5nm and below by inserting a W layer with optimum thickness at the interface between La2O3 high-k gate dielectric and the TiN gate metal.
|Title of host publication||Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications|
|Publisher||Electrochemical Society Inc.|
|Number of pages||4|
|Publication status||Published - 2011|
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