Effect with high density nano dot type storage layer structure on 20nm planar NAND flash memory characteristics

Takeshi Sasaki, Masakazu Muraguchi, Moon Sik Seo, Sung Kye Park, Tetsuo Endoh

Research output: Contribution to journalArticlepeer-review

Abstract

The merits, concerns and design principle for the future nano dot (ND) type NAND flash memory cell are clarified, by considering the effect of storage layer structure on NAND flash memory characteristics. The characteristics of the ND cell for a NAND flash memory in comparison with the floating gate type (FG) is comprehensively studied through the read, erase, program operation, and the cell to cell interference with device simulation. Although the degradation of the read throughput (0.7% reduction of the cell current) and slower program time (26% smaller programmed threshold voltage shift) with high density (10×1012cm-2) ND NAND are still concerned, the suppress of the cell to cell interference with high density (10×10 12cm-2) plays the most important part for scaling and multi-level cell (MLC) operation in comparison with the FG NAND. From these results, the design knowledge is shown to require the control of the number of nano dots rather than the higher nano dot density, from the viewpoint of increasing its memory capacity by MLC operation and suppressing threshold voltage variability caused by the number of dots in the storage layer. Moreover, in order to increase its memory capacity, it is shown the tunnel oxide thickness with ND should be designed thicker (>3 nm) than conventional designed ND cell for programming/erasing with direct tunneling mechanism.

Original languageEnglish
Article number04ED17
JournalJapanese journal of applied physics
Volume53
Issue number4 SPEC. ISSUE
DOIs
Publication statusPublished - 2014 Apr

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)

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