The conduction mechanism of HfSiON stacked-gate dielectric films after a spike annealing is investigated. FETs fabricated using the Damascene process is used to evaluate the electronic characteristics of a stacked-gate dielectric film. The effect of an additional spike annealing after the TiN gate electrode fabrication on the conductivity is analyzed. The electron current over the entire range of gate voltage is increased, while the hole current remains unchanged. The TAT and Schottky analyses derive a consistent energy level of the intermediate trap centers contributing to the electron conduction. The average lifetime is improved by annealing. However, the spike annealing does not change the slope of the TDDB Weibull plots. The average lifetime is improved by annealing. From NBTI analyses, the threshold voltages displayed linearly shifts with increasing injection charge concentration, both with and without the spike annealing. The slope of the threshold voltage shift is defined as a degradation rate.