Effect of annealing on electronic characteristics of HfSiON films fabricated by Damascene gate process

K. Yamabe, K. Murata, T. Hayashi, T. Tamura, M. Sato, A. Uedono, K. Shiraishi, N. Umezawa, T. Chikyow, H. Watanabe, Y. Nara, Y. Ohji, S. Miyazaki, K. Yamada, R. Hasunuma

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The conduction mechanism of HfSiON stacked-gate dielectric films after a spike annealing is investigated. FETs fabricated using the Damascene process is used to evaluate the electronic characteristics of a stacked-gate dielectric film. The effect of an additional spike annealing after the TiN gate electrode fabrication on the conductivity is analyzed. The electron current over the entire range of gate voltage is increased, while the hole current remains unchanged. The TAT and Schottky analyses derive a consistent energy level of the intermediate trap centers contributing to the electron conduction. The average lifetime is improved by annealing. However, the spike annealing does not change the slope of the TDDB Weibull plots. The average lifetime is improved by annealing. From NBTI analyses, the threshold voltages displayed linearly shifts with increasing injection charge concentration, both with and without the spike annealing. The slope of the threshold voltage shift is defined as a degradation rate.

Original languageEnglish
Title of host publicationECS Transactions - Physics and Technology of High-k Gate Dielectrics 6
Pages521-526
Number of pages6
Edition5
DOIs
Publication statusPublished - 2008 Dec 1
EventPhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting - Honolulu, HI, United States
Duration: 2008 Oct 132008 Oct 15

Publication series

NameECS Transactions
Number5
Volume16
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherPhysics and Technology of High-k Gate Dielectrics 6 - 214th ECS Meeting
CountryUnited States
CityHonolulu, HI
Period08/10/1308/10/15

ASJC Scopus subject areas

  • Engineering(all)

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