Dynamically rule-programmable VLSI processor for fully-parallel inference

T. Hanyu, K. Takeda, T. Higuchi

Research output: Contribution to journalArticlepeer-review

Abstract

A dynamically rule-programmable fully-parallel inference accelerator VLSI is proposed for real-time rule-based systems with large databases. The direct multiple-valued encoding of each attribute value in rules and the threshold voltage programming of floating-gate MOS devices make a high-performance VLSI possible. The improvement of performance compared with the conventional binary implementation is demonstrated.

Original languageEnglish
Pages (from-to)695-697
Number of pages3
JournalElectronics Letters
Volume28
Issue number7
DOIs
Publication statusPublished - 1992 Mar

Keywords

  • Large-scale integration
  • Parallel processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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