Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment

Research output: Contribution to conferencePaper

1 Citation (Scopus)

Abstract

Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.

Original languageEnglish
Pages155-158
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Event2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China
Duration: 2006 Nov 132006 Nov 15

Other

Other2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
CountryChina
CityHangzhou
Period06/11/1306/11/15

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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    Hariyama, M., Muthumala, W. H., & Kameyama, M. (2006). Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment. 155-158. Paper presented at 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, Hangzhou, China. https://doi.org/10.1109/ASSCC.2006.357874