Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment

Masanori Hariyama; Waidyasooriya Hasitha Muthumala; Michitaka Kameyama

doi:10.1109/ASSCC.2006.357874

Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment

Masanori Hariyama, Waidyasooriya Hasitha Muthumala, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Contribution to conference › Paper › peer-review

1 Citation (Scopus)

Abstract

Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.

Original language	English
Pages	155-158
Number of pages	4
DOIs	https://doi.org/10.1109/ASSCC.2006.357874
Publication status	Published - 2006 Dec 1
Event	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 2006 Nov 13 → 2006 Nov 15

Other

Other	2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006
Country/Territory	China
City	Hangzhou
Period	06/11/13 → 06/11/15

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/ASSCC.2006.357874

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abstract = "Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.",

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AU - Hariyama, Masanori

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AU - Kameyama, Michitaka

PY - 2006/12/1

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AB - Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.

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Dynamically reconfigurable gate array based on fine-grained switch elements and its CAD environment

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