Abstract
Dynamically programmable gate arrays (DPGAs) promise lower-cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One important issue on DPGAs is the large amount of configuration memory, which leads to area-inefficient implementation and large static power dissipation. This paper presents novel architecture of a switch block to overcome the required capacity of configuration memory. Our main idea is to exploit redundancy between different contexts by using a fine-grained switch element. The proposed MC-FPGA is designed in a 0.18μm CMOS technology. Its maximum clock frequency and the context switching frequency are measured to be 310MHz and 272MHz, respectively. The area of the proposed MC-FPGA is reduced to 45% of a typical MC-FPGA under a constraint of 8 contexts.
Original language | English |
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Pages | 155-158 |
Number of pages | 4 |
DOIs | |
Publication status | Published - 2006 Dec 1 |
Event | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 - Hangzhou, China Duration: 2006 Nov 13 → 2006 Nov 15 |
Other
Other | 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006 |
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Country/Territory | China |
City | Hangzhou |
Period | 06/11/13 → 06/11/15 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials