Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit

Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama

Research output: Contribution to conferencePaperpeer-review

11 Citations (Scopus)


This paper presents a fine-grain pipelined asynchronous circuit that uses a mixture of dual-rail and single-rail logic. Dual-rail logic is limited to construct a stable critical path. Based on this critical path, the handshake control circuit is greatly simplified, which improves the performance of speed and power consumption. On the other hand, non-critical paths are composed of single-rail logic which has small logic overhead and the entire pipelined circuit has no intermediate registers or latches. To evaluate the proposed design method, an array style multiplier is designed and simulated in a 65nm design rule. The multiplier works as high as 4.35G data-set/s. Compared to the classical synchronous circuit, the proposed circuit has no active power consumption when there are no data operation. Even the circuits work at peak speed, the proposed circuit still reduces the power consumption by 35%.

Original languageEnglish
Number of pages4
Publication statusPublished - 2012 Sep 28
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 2012 May 202012 May 23


Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
Country/TerritoryKorea, Republic of


  • asynchronous circuit
  • dual-rail logic
  • single-rail logic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


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