Dual-rail multiple-valued current-mode VLSI with biasing current sources

T. Ike, T. Hanyu, M. Kameyama

Research output: Contribution to journalConference article

8 Citations (Scopus)

Abstract

A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-μm CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.

Original languageEnglish
Pages (from-to)21-26
Number of pages6
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2001 Jan 1
Event31st IEEE International Symposium on Multiple-Valued Logic (ISMVL 2001) - Warsaw, Poland
Duration: 2001 May 222001 May 24

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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