Dual metal gate FinFET integration by Ta/Mo diffusion technology for Vt reduction and multi-Vt CMOS application

Takashi Matsukawa, Kazuhiko Endo, Yongxun Liu, Shin Ichi O'Uchi, Meishoku Masahara, Yuki Ishikawa, Hiromi Yamauchi, Junichi Tsukada, Ken Ichi Ishii, Kunihiro Sakamoto, Eiichi Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Dual metal gate CMOS FinFETs have been integrated successfully by the Ta/Mo interdiffusion technology. For the first time, low-Vt CMOS FinFETs representing on-current enhancement and high-Vt CMOS FinFETs reducing stand-by power dramatically, namely multi-Vt CMOS FinFETs, are demonstrated by selecting Ta/Mo gates for n or pMOS FinFETs with non-doped fin channels. The dual metal gate FinFET SRAM with a low-Vt configuration is demonstrated with excellent noise margins at a reduced supply voltage.

Original languageEnglish
Title of host publicationESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages282-285
Number of pages4
ISBN (Print)9781424423644
DOIs
Publication statusPublished - 2008 Jan 1
Externally publishedYes
EventESSDERC 2008 - 38th European Solid-State Device Research Conference - Edinburgh, Scotland, United Kingdom
Duration: 2008 Sep 152008 Sep 19

Publication series

NameESSDERC 2008 - Proceedings of the 38th European Solid-State Device Research Conference

Other

OtherESSDERC 2008 - 38th European Solid-State Device Research Conference
CountryUnited Kingdom
CityEdinburgh, Scotland
Period08/9/1508/9/19

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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