DSP-specific field-programmable VLSI and its CAD environment

Masanori Hariyama; Sho Ogata; Michitaka Kameyama

doi:10.1109/MWSCAS.2005.1594185

DSP-specific field-programmable VLSI and its CAD environment

Masanori Hariyama, Sho Ogata, Michitaka Kameyama

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A field-programmable VLSI processor (FPVLSI) is proposed based on a bit-serial pipeline architecture and a mesh network that greatly reduce complexity of a programmable interconnection network. An area-efficient shift-register-based cell is also proposed based on regularity of bit-serial operation. To minimize an inter-cell network, functionality of a programmable switch block is realized only by programming cells. Moreover, direct allocation of a control/data flow graph (CDFG) is introduced to localize data transfer. As a result, an ultra-highly-parallel cellular array is achieved that can efficiently exploit high parallelism of DSP applications. The FPVLSI is designed in a 0.18μm CMOS design rule. Its performance at 700MHz is 4.7 to 9 times higher than that of a conventional FPGA in typical applications under constraints of the same chip area and the same power consumption.

Original language	English
Title of host publication	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Pages	651-654
Number of pages	4
Volume	2005
DOIs	https://doi.org/10.1109/MWSCAS.2005.1594185
Publication status	Published - 2005 Dec 1
Event	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005 - Cincinnati, OH, United States Duration: 2005 Aug 7 → 2005 Aug 10

Other

Other	2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005
Country/Territory	United States
City	Cincinnati, OH
Period	05/8/7 → 05/8/10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/MWSCAS.2005.1594185

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Hariyama, M, Ogata, S & Kameyama, M 2005, DSP-specific field-programmable VLSI and its CAD environment. in 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005. vol. 2005, 1594185, pp. 651-654, 2005 IEEE International 48th Midwest Symposium on Circuits and Systems, MWSCAS 2005, Cincinnati, OH, United States, 05/8/7. https://doi.org/10.1109/MWSCAS.2005.1594185

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N2 - A field-programmable VLSI processor (FPVLSI) is proposed based on a bit-serial pipeline architecture and a mesh network that greatly reduce complexity of a programmable interconnection network. An area-efficient shift-register-based cell is also proposed based on regularity of bit-serial operation. To minimize an inter-cell network, functionality of a programmable switch block is realized only by programming cells. Moreover, direct allocation of a control/data flow graph (CDFG) is introduced to localize data transfer. As a result, an ultra-highly-parallel cellular array is achieved that can efficiently exploit high parallelism of DSP applications. The FPVLSI is designed in a 0.18μm CMOS design rule. Its performance at 700MHz is 4.7 to 9 times higher than that of a conventional FPGA in typical applications under constraints of the same chip area and the same power consumption.

AB - A field-programmable VLSI processor (FPVLSI) is proposed based on a bit-serial pipeline architecture and a mesh network that greatly reduce complexity of a programmable interconnection network. An area-efficient shift-register-based cell is also proposed based on regularity of bit-serial operation. To minimize an inter-cell network, functionality of a programmable switch block is realized only by programming cells. Moreover, direct allocation of a control/data flow graph (CDFG) is introduced to localize data transfer. As a result, an ultra-highly-parallel cellular array is achieved that can efficiently exploit high parallelism of DSP applications. The FPVLSI is designed in a 0.18μm CMOS design rule. Its performance at 700MHz is 4.7 to 9 times higher than that of a conventional FPGA in typical applications under constraints of the same chip area and the same power consumption.

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Y2 - 7 August 2005 through 10 August 2005

ER -

DSP-specific field-programmable VLSI and its CAD environment

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