Drastic reduction of keep-out-zone in 3D-IC by local stress suppression with negative-CTE filler

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Three-dimensional IC (3D IC) is a promising method to enhance IC performance. Conventional 3D ICs consist of vertically stacked several thin IC chips those are electrically connected with lots of through-Si vias (TSVs) and metal microbumps. Metal microbumps are surrounded by organic adhesive. An epoxy-based material, so-called underfill, has been widely used to fill the gap between several chips. In general, coefficient of thermal expansion (CTE) of the underfill material is larger than that of metal microbumps. This CTE mismatch induces local bending stress in thinned IC chips. This local bending stress would affect CMOS circuit in thinned IC chips. Therefore, we should suppress the local bending stress to realize 3D IC with high reliability. In this work, we propose a novel underfill with negative-CTE filler which can suppress the local bending stress in 3D IC.

Original languageEnglish
Title of host publication2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781509013999
DOIs
Publication statusPublished - 2017 Jul 5
Event2016 IEEE International 3D Systems Integration Conference, 3DIC 2016 - San Francisco, United States
Duration: 2016 Nov 82016 Nov 11

Publication series

Name2016 IEEE International 3D Systems Integration Conference, 3DIC 2016

Other

Other2016 IEEE International 3D Systems Integration Conference, 3DIC 2016
CountryUnited States
CitySan Francisco
Period16/11/816/11/11

Keywords

  • 3D IC
  • local bending stress
  • microbump
  • underfill

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electronic, Optical and Magnetic Materials
  • Computer Networks and Communications

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