DRAM-cell-based multiple-valued logic-in-memory VLSI with charge addition and charge storage

Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

Abstract

A multiple-valued logic-in-memory VLSI with fast reprogrammability is proposed to realize transfer-bottle-neck-free VLSI systems. A basic component, in which a dynamic storage function and a multiple-valued threshold-literal function are merged, can be simply implemented by charge addition and charge storage with a DRAM-cell-based circuit structure. Any logic circuits with multiple-valued inputs and binary outputs can be realized by the combination of the basic components and logic-value conversion. As a typical example, a fully parallel magnitude comparator between three-valued input and stored words is designed by using the proposed logic-in-memory VLSI architecture. Its performance is superior to that of a corresponding binary implementation by using HSPICE simulation under a 0.5 - μm CMOS technology.

Original languageEnglish
Pages (from-to)423-429
Number of pages7
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2000 Jan 1
EventISMVL'2000 - 30th IEEE International Symposium on Multiple-Valued Logic - Portland, OR, USA
Duration: 2000 May 232000 May 25

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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