Since mechanical stress and strain change both electronic functions and reliability of LSI chips, it has become strongly important to control the residual stress and strain in them to assure their reliable performance. In this study, the authors discuss the stress distribution in chips stacked using area-arrayed metallic bumps. The average residual stress in the stacked two chips changes drastically depending on the distance from a bending neutral axis of the stacked structure, and the local residual stress also varies depending on the relative position of bumps between an upper and a bottom interconnection layer. However, the residual stress of the top chip with a free surface is not affected by the bump alignment in lower interconnection layers. It is very important, therefore, to optimize the thickness of a chip and other structural factors as mentioned above to control not only the average residual stress but also the amplitude of the periodic stress. Finally, the estimated stress distribution in the stacked two chips was proved in detail by the experiment using stress-sensing chips with 2-μm long strain gauges consisted of single-crystalline Si.