Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array

Wang Luzhou, Kentaro Sano, Satoru Yamamoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

This paper presents a domain-specific language for stencil computation (DSLSC) and its compiler for our FPGA-based systolic computational-memory array (SCMA). In DSLSC, we can program stencil computations by describing their mathematical form instead of writing explicit procedure optimally. The compiler automatically parallelizes stencil computations for processing elements (PEs) of SCMA, and schedules multiply-and-add operations for PEs considering data-reference delay via a local memory or communication FIFOs between PEs. For arbitrary grid-sizes of 2D Jacobi compilation with 3x3 and 5x5 stencils, the compiler achieves high utilization of PEs, 85.6 % and 92.18 %, which are close to 87.5 % and 93.75 % for ideal cases, respectively.

Original languageEnglish
Title of host publicationReconfigurable Computing
Subtitle of host publicationArchitectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings
Pages26-39
Number of pages14
DOIs
Publication statusPublished - 2012 Apr 11
Event8th International Symposium on Applied Reconfigurable Computing, ARC 2012 - Hong Kong, China
Duration: 2012 Mar 192012 Mar 23

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume7199 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349

Other

Other8th International Symposium on Applied Reconfigurable Computing, ARC 2012
CountryChina
CityHong Kong
Period12/3/1912/3/23

Keywords

  • compiler
  • domain-specific language
  • stencil computation
  • systolic computational-memory architecture

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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    Luzhou, W., Sano, K., & Yamamoto, S. (2012). Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings (pp. 26-39). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 7199 LNCS). https://doi.org/10.1007/978-3-642-28365-9_3