Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array

Wang Luzhou; Kentaro Sano; Satoru Yamamoto

doi:10.1007/978-3-642-28365-9_3

Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array

Wang Luzhou, Kentaro Sano, Satoru Yamamoto

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper presents a domain-specific language for stencil computation (DSLSC) and its compiler for our FPGA-based systolic computational-memory array (SCMA). In DSLSC, we can program stencil computations by describing their mathematical form instead of writing explicit procedure optimally. The compiler automatically parallelizes stencil computations for processing elements (PEs) of SCMA, and schedules multiply-and-add operations for PEs considering data-reference delay via a local memory or communication FIFOs between PEs. For arbitrary grid-sizes of 2D Jacobi compilation with 3x3 and 5x5 stencils, the compiler achieves high utilization of PEs, 85.6 % and 92.18 %, which are close to 87.5 % and 93.75 % for ideal cases, respectively.

Original language	English
Title of host publication	Reconfigurable Computing
Subtitle of host publication	Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings
Pages	26-39
Number of pages	14
DOIs	https://doi.org/10.1007/978-3-642-28365-9_3
Publication status	Published - 2012
Event	8th International Symposium on Applied Reconfigurable Computing, ARC 2012 - Hong Kong, China Duration: 2012 Mar 19 → 2012 Mar 23

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	7199 LNCS
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	8th International Symposium on Applied Reconfigurable Computing, ARC 2012
Country	China
City	Hong Kong
Period	12/3/19 → 12/3/23

Keywords

compiler
domain-specific language
stencil computation
systolic computational-memory architecture

ASJC Scopus subject areas

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/978-3-642-28365-9_3

Fingerprint Dive into the research topics of 'Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array'. Together they form a unique fingerprint.

Cite this

Luzhou, W., Sano, K., & Yamamoto, S. (2012). Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings (pp. 26-39). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 7199 LNCS). https://doi.org/10.1007/978-3-642-28365-9_3

Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. / Luzhou, Wang; Sano, Kentaro; Yamamoto, Satoru.

Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. p. 26-39 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 7199 LNCS).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Luzhou, W, Sano, K & Yamamoto, S 2012, Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. in Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 7199 LNCS, pp. 26-39, 8th International Symposium on Applied Reconfigurable Computing, ARC 2012, Hong Kong, China, 12/3/19. https://doi.org/10.1007/978-3-642-28365-9_3

Luzhou W, Sano K, Yamamoto S. Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. In Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. p. 26-39. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). https://doi.org/10.1007/978-3-642-28365-9_3

Luzhou, Wang ; Sano, Kentaro ; Yamamoto, Satoru. / Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array. Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Proceedings. 2012. pp. 26-39 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{af9b1f02c3454aa0acd30d1172006a03,

title = "Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array",

abstract = "This paper presents a domain-specific language for stencil computation (DSLSC) and its compiler for our FPGA-based systolic computational-memory array (SCMA). In DSLSC, we can program stencil computations by describing their mathematical form instead of writing explicit procedure optimally. The compiler automatically parallelizes stencil computations for processing elements (PEs) of SCMA, and schedules multiply-and-add operations for PEs considering data-reference delay via a local memory or communication FIFOs between PEs. For arbitrary grid-sizes of 2D Jacobi compilation with 3x3 and 5x5 stencils, the compiler achieves high utilization of PEs, 85.6 % and 92.18 %, which are close to 87.5 % and 93.75 % for ideal cases, respectively.",

keywords = "compiler, domain-specific language, stencil computation, systolic computational-memory architecture",

author = "Wang Luzhou and Kentaro Sano and Satoru Yamamoto",

year = "2012",

doi = "10.1007/978-3-642-28365-9_3",

language = "English",

isbn = "9783642283642",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

pages = "26--39",

booktitle = "Reconfigurable Computing",

}

TY - GEN

T1 - Domain-specific language and compiler for stencil computation on FPGA-based systolic computational-memory array

AU - Luzhou, Wang

AU - Sano, Kentaro

AU - Yamamoto, Satoru

PY - 2012

Y1 - 2012

N2 - This paper presents a domain-specific language for stencil computation (DSLSC) and its compiler for our FPGA-based systolic computational-memory array (SCMA). In DSLSC, we can program stencil computations by describing their mathematical form instead of writing explicit procedure optimally. The compiler automatically parallelizes stencil computations for processing elements (PEs) of SCMA, and schedules multiply-and-add operations for PEs considering data-reference delay via a local memory or communication FIFOs between PEs. For arbitrary grid-sizes of 2D Jacobi compilation with 3x3 and 5x5 stencils, the compiler achieves high utilization of PEs, 85.6 % and 92.18 %, which are close to 87.5 % and 93.75 % for ideal cases, respectively.

AB - This paper presents a domain-specific language for stencil computation (DSLSC) and its compiler for our FPGA-based systolic computational-memory array (SCMA). In DSLSC, we can program stencil computations by describing their mathematical form instead of writing explicit procedure optimally. The compiler automatically parallelizes stencil computations for processing elements (PEs) of SCMA, and schedules multiply-and-add operations for PEs considering data-reference delay via a local memory or communication FIFOs between PEs. For arbitrary grid-sizes of 2D Jacobi compilation with 3x3 and 5x5 stencils, the compiler achieves high utilization of PEs, 85.6 % and 92.18 %, which are close to 87.5 % and 93.75 % for ideal cases, respectively.

KW - compiler

KW - domain-specific language

KW - stencil computation

KW - systolic computational-memory architecture

UR - http://www.scopus.com/inward/record.url?scp=84859460630&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84859460630&partnerID=8YFLogxK

U2 - 10.1007/978-3-642-28365-9_3

DO - 10.1007/978-3-642-28365-9_3

M3 - Conference contribution

AN - SCOPUS:84859460630

SN - 9783642283642

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 26

EP - 39

BT - Reconfigurable Computing

T2 - 8th International Symposium on Applied Reconfigurable Computing, ARC 2012

Y2 - 19 March 2012 through 23 March 2012

ER -