Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization

Ryohei Sato; Koichi Kakimoto; Wataru Saito; Shin Ichi Nishizawa

doi:10.1109/ISPSD46842.2020.9170035

Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization

Ryohei Sato, Koichi Kakimoto, Wataru Saito, Shin Ichi Nishizawa

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.

Original language	English
Title of host publication	Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	494-497
Number of pages	4
ISBN (Electronic)	9781728148366
DOIs	https://doi.org/10.1109/ISPSD46842.2020.9170035
Publication status	Published - 2020 Sept
Externally published	Yes
Event	32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 - Virtual, Online, Austria Duration: 2020 Sept 13 → 2020 Sept 18

Publication series

Name	Proceedings of the International Symposium on Power Semiconductor Devices and ICs
Volume	2020-September
ISSN (Print)	1063-6854

Conference

Conference	32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
Country/Territory	Austria
City	Virtual, Online
Period	20/9/13 → 20/9/18

Keywords

IGBT
Si wafer
dislocation
thermal budget process

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/ISPSD46842.2020.9170035

Cite this

Sato, R., Kakimoto, K., Saito, W., & Nishizawa, S. I. (2020). Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. In Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 (pp. 494-497). [9170035] (Proceedings of the International Symposium on Power Semiconductor Devices and ICs; Vol. 2020-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPSD46842.2020.9170035

Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. / Sato, Ryohei; Kakimoto, Koichi; Saito, Wataru et al.

Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 494-497 9170035 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs; Vol. 2020-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sato, R, Kakimoto, K, Saito, W & Nishizawa, SI 2020, Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. in Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020., 9170035, Proceedings of the International Symposium on Power Semiconductor Devices and ICs, vol. 2020-September, Institute of Electrical and Electronics Engineers Inc., pp. 494-497, 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020, Virtual, Online, Austria, 20/9/13. https://doi.org/10.1109/ISPSD46842.2020.9170035

Sato R, Kakimoto K, Saito W, Nishizawa SI. Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. In Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 494-497. 9170035. (Proceedings of the International Symposium on Power Semiconductor Devices and ICs). doi: 10.1109/ISPSD46842.2020.9170035

Sato, Ryohei ; Kakimoto, Koichi ; Saito, Wataru et al. / Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 494-497 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs).

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title = "Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization",

abstract = "This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.",

keywords = "IGBT, Si wafer, dislocation, thermal budget process",

author = "Ryohei Sato and Koichi Kakimoto and Wataru Saito and Nishizawa, {Shin Ichi}",

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N2 - This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.

AB - This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.

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Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization

Abstract

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Keywords

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