Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with Vfb controllability

K. Kakushima, T. Koyanagi, D. Kitayama, M. Kouda, J. Song, T. Kawanago, M. Mamatrishat, K. Tachi, M. K. Bera, P. Ahmet, H. Nohira, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, K. Yamada, H. Iwai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (V fb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the Vfb to positive direction.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages69-70
Number of pages2
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 2010 Jun 152010 Jun 17

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
CountryUnited States
CityHonolulu, HI
Period10/6/1510/6/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V<sub>fb</sub> controllability'. Together they form a unique fingerprint.

Cite this