Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with Vfb controllability

K. Kakushima; T. Koyanagi; D. Kitayama; M. Kouda; J. Song; T. Kawanago; M. Mamatrishat; K. Tachi; M. K. Bera; P. Ahmet; H. Nohira; K. Tsutsui; A. Nishiyama; N. Sugii; K. Natori; T. Hattori; K. Yamada; H. Iwai

doi:10.1109/VLSIT.2010.5556115

Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V_fb controllability

K. Kakushima, T. Koyanagi, D. Kitayama, M. Kouda, J. Song, T. Kawanago, M. Mamatrishat, K. Tachi, M. K. Bera, P. Ahmet, H. Nohira, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, K. Yamada, H. Iwai

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Citations (Scopus)

Abstract

A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (k_av) of 17.4 has been obtained and an extremely low gate leakage current (J_g) of 0.65 A/cm². The flatband voltage (V _fb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the V_fb to positive direction.

Original language	English
Title of host publication	2010 Symposium on VLSI Technology, VLSIT 2010
Pages	69-70
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2010.5556115
Publication status	Published - 2010
Externally published	Yes
Event	2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States Duration: 2010 Jun 15 → 2010 Jun 17

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2010 Symposium on VLSI Technology, VLSIT 2010
Country/Territory	United States
City	Honolulu, HI
Period	10/6/15 → 10/6/17

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2010.5556115

Cite this

Kakushima, K., Koyanagi, T., Kitayama, D., Kouda, M., Song, J., Kawanago, T., Mamatrishat, M., Tachi, K., Bera, M. K., Ahmet, P., Nohira, H., Tsutsui, K., Nishiyama, A., Sugii, N., Natori, K., Hattori, T., Yamada, K., & Iwai, H. (2010). Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V_fb controllability. In 2010 Symposium on VLSI Technology, VLSIT 2010 (pp. 69-70). [5556115] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2010.5556115

Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V_fb controllability. / Kakushima, K.; Koyanagi, T.; Kitayama, D.; Kouda, M.; Song, J.; Kawanago, T.; Mamatrishat, M.; Tachi, K.; Bera, M. K.; Ahmet, P.; Nohira, H.; Tsutsui, K.; Nishiyama, A.; Sugii, N.; Natori, K.; Hattori, T.; Yamada, K.; Iwai, H.

2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 69-70 5556115 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kakushima, K, Koyanagi, T, Kitayama, D, Kouda, M, Song, J, Kawanago, T, Mamatrishat, M, Tachi, K, Bera, MK, Ahmet, P, Nohira, H, Tsutsui, K, Nishiyama, A, Sugii, N, Natori, K, Hattori, T, Yamada, K & Iwai, H 2010, Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V_fb controllability. in 2010 Symposium on VLSI Technology, VLSIT 2010., 5556115, Digest of Technical Papers - Symposium on VLSI Technology, pp. 69-70, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 10/6/15. https://doi.org/10.1109/VLSIT.2010.5556115

Kakushima, K. ; Koyanagi, T. ; Kitayama, D. ; Kouda, M. ; Song, J. ; Kawanago, T. ; Mamatrishat, M. ; Tachi, K. ; Bera, M. K. ; Ahmet, P. ; Nohira, H. ; Tsutsui, K. ; Nishiyama, A. ; Sugii, N. ; Natori, K. ; Hattori, T. ; Yamada, K. ; Iwai, H. / Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with V_fb controllability. 2010 Symposium on VLSI Technology, VLSIT 2010. 2010. pp. 69-70 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (V fb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the Vfb to positive direction.",

author = "K. Kakushima and T. Koyanagi and D. Kitayama and M. Kouda and J. Song and T. Kawanago and M. Mamatrishat and K. Tachi and Bera, {M. K.} and P. Ahmet and H. Nohira and K. Tsutsui and A. Nishiyama and N. Sugii and K. Natori and T. Hattori and K. Yamada and H. Iwai",

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AU - Koyanagi, T.

AU - Kitayama, D.

AU - Kouda, M.

AU - Song, J.

AU - Kawanago, T.

AU - Mamatrishat, M.

AU - Tachi, K.

AU - Bera, M. K.

AU - Ahmet, P.

AU - Nohira, H.

AU - Tsutsui, K.

AU - Nishiyama, A.

AU - Sugii, N.

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AU - Hattori, T.

AU - Yamada, K.

AU - Iwai, H.

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