TY - GEN
T1 - Direct contact of high-k/Si gate stack for EOT below 0.7 nm using LaCe-silicate layer with Vfb controllability
AU - Kakushima, K.
AU - Koyanagi, T.
AU - Kitayama, D.
AU - Kouda, M.
AU - Song, J.
AU - Kawanago, T.
AU - Mamatrishat, M.
AU - Tachi, K.
AU - Bera, M. K.
AU - Ahmet, P.
AU - Nohira, H.
AU - Tsutsui, K.
AU - Nishiyama, A.
AU - Sugii, N.
AU - Natori, K.
AU - Hattori, T.
AU - Yamada, K.
AU - Iwai, H.
PY - 2010
Y1 - 2010
N2 - A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (V fb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the Vfb to positive direction.
AB - A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (V fb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the Vfb to positive direction.
UR - http://www.scopus.com/inward/record.url?scp=77957861958&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77957861958&partnerID=8YFLogxK
U2 - 10.1109/VLSIT.2010.5556115
DO - 10.1109/VLSIT.2010.5556115
M3 - Conference contribution
AN - SCOPUS:77957861958
SN - 9781424476374
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 69
EP - 70
BT - 2010 Symposium on VLSI Technology, VLSIT 2010
T2 - 2010 Symposium on VLSI Technology, VLSIT 2010
Y2 - 15 June 2010 through 17 June 2010
ER -