Die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems

Kang Wook Lee, Yuki Ohara, Kouji Kiyoyama, Ji Cheol Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

20 Citations (Scopus)

Abstract

We proposed a die-level 3-D integration technology for rapid prototyping of high-performance multifunctionality hetero-integrated systems. Commercially available 2-D chips with different functions and sizes could be processed and integrated in die level. To realize the die-level 3-D integration, fine-sized backside through silicon via (TSV) and novel detachable technologies are developed. In this paper, we demonstrated a prototype 3-D stacked image sensor system using the die-level 3-D integration technology. Three different functional chips of CMOS image sensor, correlated double sampling, and analog-to-digital converter, which were fabricated by different technologies, were processed to form fine-sized backside Cu TSV of 5- m diameter and metal microbumps in die level. Each chip was sequentially stacked after evaluating the basic function to form a known-good-die 3-D stacked system. The fundamental characteristics of each functional chip were successfully evaluated in the fabricated prototype 3-D stacked image sensor system.

Original languageEnglish
Article number6601012
Pages (from-to)3842-3848
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume60
Issue number11
DOIs
Publication statusPublished - 2013

Keywords

  • Backside through silicon via (TSV)
  • die-level 3-D integration
  • hetero-integrated system

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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