Development of three-dimensional integration technology for highly parallel image-processing chip

Kang Wook Lee, Tomonori Nakamura, Katsuyuki Sakuma, Ki Tae Park, Hiroaki Shimazutsu, Nobuaki Miyakawa, Ki Yoon Kim, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Contribution to journalArticlepeer-review

49 Citations (Scopus)


A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D. integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

Original languageEnglish
Pages (from-to)2473-2477
Number of pages5
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Issue number4 B
Publication statusPublished - 2000
Externally publishedYes


  • Image sensor
  • Three dimensional (3D) integration LSI
  • Wafer-level bonding

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


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