Development of three-dimensional integration technology for highly parallel image-processing chip

Kang Wook Lee; Tomonori Nakamura; Katsuyuki Sakuma; Ki Tae Park; Hiroaki Shimazutsu; Nobuaki Miyakawa; Ki Yoon Kim; Hiroyuki Kurino; Mitsumasa Koyanagi

doi:10.1143/jjap.39.2473

Development of three-dimensional integration technology for highly parallel image-processing chip

Kang Wook Lee, Tomonori Nakamura, Katsuyuki Sakuma, Ki Tae Park, Hiroaki Shimazutsu, Nobuaki Miyakawa, Ki Yoon Kim, Hiroyuki Kurino, Mitsumasa Koyanagi

New Industry Creation Hatchery Center (NICHe)

Research output: Contribution to journal › Article › peer-review

48 Citations (Scopus)

Abstract

A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D. integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

Original language	English
Pages (from-to)	2473-2477
Number of pages	5
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	39
Issue number	4 B
DOIs	https://doi.org/10.1143/jjap.39.2473
Publication status	Published - 2000

Keywords

Image sensor
Three dimensional (3D) integration LSI
Wafer-level bonding

ASJC Scopus subject areas

Engineering(all)
Physics and Astronomy(all)

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10.1143/jjap.39.2473

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Lee, K. W., Nakamura, T., Sakuma, K., Park, K. T., Shimazutsu, H., Miyakawa, N., Kim, K. Y., Kurino, H., & Koyanagi, M. (2000). Development of three-dimensional integration technology for highly parallel image-processing chip. Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, 39(4 B), 2473-2477. https://doi.org/10.1143/jjap.39.2473

Development of three-dimensional integration technology for highly parallel image-processing chip. / Lee, Kang Wook; Nakamura, Tomonori; Sakuma, Katsuyuki; Park, Ki Tae; Shimazutsu, Hiroaki; Miyakawa, Nobuaki; Kim, Ki Yoon; Kurino, Hiroyuki; Koyanagi, Mitsumasa.

In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol. 39, No. 4 B, 2000, p. 2473-2477.

Research output: Contribution to journal › Article › peer-review

Lee, KW, Nakamura, T, Sakuma, K, Park, KT, Shimazutsu, H, Miyakawa, N, Kim, KY, Kurino, H & Koyanagi, M 2000, 'Development of three-dimensional integration technology for highly parallel image-processing chip', Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, vol. 39, no. 4 B, pp. 2473-2477. https://doi.org/10.1143/jjap.39.2473

Lee, Kang Wook ; Nakamura, Tomonori ; Sakuma, Katsuyuki ; Park, Ki Tae ; Shimazutsu, Hiroaki ; Miyakawa, Nobuaki ; Kim, Ki Yoon ; Kurino, Hiroyuki ; Koyanagi, Mitsumasa. / Development of three-dimensional integration technology for highly parallel image-processing chip. In: Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers. 2000 ; Vol. 39, No. 4 B. pp. 2473-2477.

@article{530a479071a34729b41a0f3c0676f113,

title = "Development of three-dimensional integration technology for highly parallel image-processing chip",

abstract = "A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D. integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.",

keywords = "Image sensor, Three dimensional (3D) integration LSI, Wafer-level bonding",

author = "Lee, {Kang Wook} and Tomonori Nakamura and Katsuyuki Sakuma and Park, {Ki Tae} and Hiroaki Shimazutsu and Nobuaki Miyakawa and Kim, {Ki Yoon} and Hiroyuki Kurino and Mitsumasa Koyanagi",

year = "2000",

doi = "10.1143/jjap.39.2473",

language = "English",

volume = "39",

pages = "2473--2477",

journal = "Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes",

issn = "0021-4922",

publisher = "Japan Society of Applied Physics",

number = "4 B",

}

TY - JOUR

T1 - Development of three-dimensional integration technology for highly parallel image-processing chip

AU - Lee, Kang Wook

AU - Nakamura, Tomonori

AU - Sakuma, Katsuyuki

AU - Park, Ki Tae

AU - Shimazutsu, Hiroaki

AU - Miyakawa, Nobuaki

AU - Kim, Ki Yoon

AU - Kurino, Hiroyuki

AU - Koyanagi, Mitsumasa

PY - 2000

Y1 - 2000

N2 - A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D. integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

AB - A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D. integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

KW - Image sensor

KW - Three dimensional (3D) integration LSI

KW - Wafer-level bonding

UR - http://www.scopus.com/inward/record.url?scp=0033717508&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033717508&partnerID=8YFLogxK

U2 - 10.1143/jjap.39.2473

DO - 10.1143/jjap.39.2473

M3 - Article

AN - SCOPUS:0033717508

VL - 39

SP - 2473

EP - 2477

JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes

SN - 0021-4922

IS - 4 B

ER -

Development of three-dimensional integration technology for highly parallel image-processing chip

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Keywords

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