Development of FeRAM circuit technologies

Hiroki Koike, Tohru Miwa, Junichi Yamada, Hideo Toyoshima

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes our circuit technologies that can be used to obtain fast and large-capacity FeRAMs with high reliability. The Non-driven Cell Plate Line Write/Read Scheme (NDP Scheme) offers a fast access time equivalent to that of DRAMs. This scheme makes it possible to access memory cells without having to drive the highly capacitive cell plate line, thus reducing write/read delay time. The Self-Reference Read Scheme is used to produce highly reliable FeRAMs, because it avoids the read voltage fluctuation, due to fatigue, imprint, and insufficient retention in the ferroelectric capacitors, between an accessed memory cell and the corresponding dummy memory cell. These technologies are essential for mega-bit-class FeRAMs.

Original languageEnglish
Pages (from-to)231-234
Number of pages4
JournalNEC Research and Development
Volume40
Issue number2
Publication statusPublished - 1999 Apr 1
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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