TY - JOUR
T1 - Development of eccentric spin coating of polymer liner for low-temperature TSV technology with ultra-fine diameter
AU - Xiong, Miao
AU - Chen, Zhiming
AU - Ding, Yingtao
AU - Kino, Hisashi
AU - Fukushima, Takafumi
AU - Tanaka, Tetsu
N1 - Funding Information:
Manuscript received November 8, 2018; accepted November 22, 2018. Date of publication December 3, 2018; date of current version January 9, 2019. This work was supported by the National Natural Science Foundation of China under Grants 61774015 and 61574016 and the 111 Project of China under Grant B14010. The review of this letter was arranged by Editor A. Naeemi. (Corresponding author: Yingtao Ding.) M. Xiong, Z. Chen, and Y. Ding are with the Beijing Institute of Technology, Beijing 100081, China (e-mail: ytd@bit.edu.cn). H. Kino is with the Frontier Research Institute for Interdisciplinary Sciences, Tohoku University, Sendai 980-8579, Japan. T. Fukushima is with the Department of Mechanical Systems Engineering, Tohoku University, Sendai 980-8579, Japan. T. Tanaka is with the Department of Biomedical Engineering, Tohoku University, Sendai 980-8579, Japan. Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2018.2884452
Publisher Copyright:
© 1980-2012 IEEE.
PY - 2019/1
Y1 - 2019/1
N2 - Through-silicon-vias (TSVs) with a diameter of 3μm and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400°C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.
AB - Through-silicon-vias (TSVs) with a diameter of 3μm and high aspect ratio of 15 are successfully fabricated based on a low-cost and low-temperature process involving spin coating of polyimide liner, electroless plating of Ni barrier/seed layer, and electroplating of Cu, which is suitable for via-middle/via-last processes that have a more stringent thermal budget. A novel eccentric spin coating technique is proposed for liner formation, which greatly improves the wafer-level uniformity and reduces the bottom dielectric thickness of the vias located close to the center of the wafer. The measured results show that the fabricated TSVs exhibit low depletion capacitance of 33 fF, low leakage current of 2.2 pA at 20 V, and good barrier property against Cu diffusion even after annealing at 400°C, indicating the feasibility of the proposed technique in high density and low area penalty 3-D large-scale integrated circuits.
KW - Eccentric spin coating
KW - high-aspect-ratio
KW - low cost
KW - low temperature
KW - through-silicon-via (TSV)
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U2 - 10.1109/LED.2018.2884452
DO - 10.1109/LED.2018.2884452
M3 - Article
AN - SCOPUS:85057886032
VL - 40
SP - 95
EP - 98
JO - IEEE Electron Device Letters
JF - IEEE Electron Device Letters
SN - 0741-3106
IS - 1
M1 - 8556087
ER -