Development of a CDS Circuit for 3-D Stacked Neural Network Chip using CMOS Analog Signal Processing

Koji Kiyoyama, Qian Zhengy, Hiroyuki Hashimoto, Hisashi Kino, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes a highly parallel analog signal processing method with three-dimensional (3-D) stacked neural network chip for convolutional and deep neural networks (CNNs and DNNs). The proposed chip has a stacked structure, which enables highly parallel mixed-signal operations like human brains with low power consumption. The product-sum operation using analog circuit in highly parallel calculation with low power supply current, but repeated calculations result in excessive noise (e.g.The offset voltage of the amplifier and 1/f noise, kT/C noise etc.) accumulation and degraded calculation accuracy. Therefore, analog signal processing with 3-D stacked multiple layers neural network chip require the noise reduction technique. In this design, correlated double sampling (CDS) is used to noise reduction technique with which reduce noise generated in the circuit. The proposed CDS circuit is designed with CMOS 0.18nm technology. As results of simulation analysis, it was confirmed that the CDS circuit reduced the offset voltage of composing amplifier and the noise voltages of the circuits placed before the CDS circuit to less than 1.25mV.

Original languageEnglish
Title of host publicationIEEE 2019 International 3D Systems Integration Conference, 3DIC 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728148700
DOIs
Publication statusPublished - 2019 Oct
Event2019 IEEE International 3D Systems Integration Conference, 3DIC 2019 - Sendai, Japan
Duration: 2019 Oct 82019 Oct 10

Publication series

NameIEEE 2019 International 3D Systems Integration Conference, 3DIC 2019

Conference

Conference2019 IEEE International 3D Systems Integration Conference, 3DIC 2019
CountryJapan
CitySendai
Period19/10/819/10/10

Keywords

  • AI chip
  • analog product-sum signal processing
  • correlated double sampling (CDS)
  • deep neural network (DNN)
  • in-memory computing NN
  • machine leaning
  • near-memory computing NN
  • neural network (NN)
  • noise reduction technique
  • stacked Neuron Chip

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Industrial and Manufacturing Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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