TY - GEN
T1 - Development of a CAD tool for 3D-FPGAs
AU - Miyamoto, Naoto
AU - Matsumoto, Yohei
AU - Koike, Hanpei
AU - Matsumura, Tadayuki
AU - Osada, Kenichi
AU - Nakagawa, Yaoko
AU - Ohmi, Tadahiro
PY - 2010/12/1
Y1 - 2010/12/1
N2 - This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.
AB - This paper presents a newly developed computer-aided design (CAD) tool for 3-dimensional field programmable gate arrays (3D-FPGAs). With this tool, primary inputs/outputs (I/Os) are packed in the configurable logic blocks (CLBs) and placed all over the 3D-FPGA. Moreover, rectangular parallelepiped confinement (RPC) and A-star (A*) search algorithms are applied to perform 3D routing, which is about 9.0 times faster than the one not introducing the algorithms, without degrading the routing quality.
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U2 - 10.1109/3DIC.2010.5751458
DO - 10.1109/3DIC.2010.5751458
M3 - Conference contribution
AN - SCOPUS:79956010325
SN - 9781457705274
T3 - IEEE 3D System Integration Conference 2010, 3DIC 2010
BT - IEEE 3D System Integration Conference 2010, 3DIC 2010
T2 - 2nd IEEE International 3D System Integration Conference, 3DIC 2010
Y2 - 16 November 2010 through 18 November 2010
ER -