Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

T. Tanaka; H. Kino; K. Kiyoyama; H. Ohno; M. Koyanagi

doi:10.1109/IITC.2013.6615594

Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

T. Tanaka, H. Kino, K. Kiyoyama, H. Ohno, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.

Original language	English
Title of host publication	Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013
DOIs	https://doi.org/10.1109/IITC.2013.6615594
Publication status	Published - 2013 Nov 4
Event	2013 16th IEEE International Interconnect Technology Conference, IITC 2013 - Kyoto, Japan Duration: 2013 Jun 13 → 2013 Jun 15

Publication series

Name	Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013

Other

Other	2013 16th IEEE International Interconnect Technology Conference, IITC 2013
Country/Territory	Japan
City	Kyoto
Period	13/6/13 → 13/6/15

ASJC Scopus subject areas

Hardware and Architecture
Control and Systems Engineering

Access to Document

10.1109/IITC.2013.6615594

Cite this

Tanaka, T., Kino, H., Kiyoyama, K., Ohno, H., & Koyanagi, M. (2013). Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology. In Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013 [6615594] (Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013). https://doi.org/10.1109/IITC.2013.6615594

Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology. / Tanaka, T.; Kino, H.; Kiyoyama, K.; Ohno, H.; Koyanagi, M.

Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013. 2013. 6615594 (Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tanaka, T , Kino, H, Kiyoyama, K, Ohno, H & Koyanagi, M 2013, Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology. in Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013., 6615594, Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013, 2013 16th IEEE International Interconnect Technology Conference, IITC 2013, Kyoto, Japan, 13/6/13. https://doi.org/10.1109/IITC.2013.6615594

Tanaka T , Kino H, Kiyoyama K, Ohno H, Koyanagi M. Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology. In Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013. 2013. 6615594. (Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013). https://doi.org/10.1109/IITC.2013.6615594

@inproceedings{cf677f023d394037af6a89d6802e8ab1,

title = "Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology",

abstract = "A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.",

author = "T. Tanaka and H. Kino and K. Kiyoyama and H. Ohno and M. Koyanagi",

year = "2013",

month = nov,

day = "4",

doi = "10.1109/IITC.2013.6615594",

language = "English",

isbn = "9781479904396",

series = "Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013",

booktitle = "Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013",

note = "2013 16th IEEE International Interconnect Technology Conference, IITC 2013 ; Conference date: 13-06-2013 Through 15-06-2013",

}

TY - GEN

T1 - Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

AU - Tanaka, T.

AU - Kino, H.

AU - Kiyoyama, K.

AU - Ohno, H.

AU - Koyanagi, M.

PY - 2013/11/4

Y1 - 2013/11/4

N2 - A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.

AB - A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.

UR - http://www.scopus.com/inward/record.url?scp=84886662068&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84886662068&partnerID=8YFLogxK

U2 - 10.1109/IITC.2013.6615594

DO - 10.1109/IITC.2013.6615594

M3 - Conference contribution

AN - SCOPUS:84886662068

SN - 9781479904396

T3 - Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013

BT - Proceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013

T2 - 2013 16th IEEE International Interconnect Technology Conference, IITC 2013

Y2 - 13 June 2013 through 15 June 2013

ER -

Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

Abstract

Publication series

Other

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this