Development of 3D-stacked reconfigurable spin logic chip using via-last backside-via 3D integration technology

T. Tanaka, H. Kino, K. Kiyoyama, H. Ohno, M. Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

A novel 3D-stacked reconfigurable spin logic chip has been successfully developed to overcome drawbacks of conventional reconfigurable LSIs. Two reconfigurable spin logic chips were carefully designed and successfully stacked using via-last backside-via technology. The fastest write speed of 5 ns was obtained in the on-chip SPRAM circuits. In order to achieve higher performance reconfigurable LSIs, parallel reconfiguration was realized with the stacked reconfigurable spin logic chips. Both via-last backside-via 3D integration and ultrafast on-chip SPRAM will bring a new reconfigurable LSI world.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013
DOIs
Publication statusPublished - 2013 Nov 4
Event2013 16th IEEE International Interconnect Technology Conference, IITC 2013 - Kyoto, Japan
Duration: 2013 Jun 132013 Jun 15

Publication series

NameProceedings of the 2013 IEEE International Interconnect Technology Conference, IITC 2013

Other

Other2013 16th IEEE International Interconnect Technology Conference, IITC 2013
CountryJapan
CityKyoto
Period13/6/1313/6/15

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering

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