Developing Efficient Implementations of Shortest Paths and Page Rank Algorithms for NEC SX-Aurora TSUBASA Architecture

I. V. Afanasyev, Vad V. Voevodin, Vl V. Voevodin, Kazuhiko Komatsu, Hiroaki Kobayashi

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

The main goal of this paper is to demonstrate that the newest generation of NEC SX-Aurora TSUBASA architecture can perform large-scale graph processing extremely efficiently. This paper proposes approaches, which can be used for the development of high-performance vector-oriented implementations of page rank and shortest paths algorithms, including vectorised graph storage format, efficient vector-friendly graph traversals, optimised cache-aware memory accesses and efficient load-balancing. The developed implementations are optimised according to the most important features and properties of SX-Aurora architecture, which allows them achieve up to 15 times better performance compared to the optimised Intel Skylake parallel implementations and up to 5 times better performance compared to NVGRAPH library implementations for Pascal GPU architecture.

Original languageEnglish
Pages (from-to)1753-1762
Number of pages10
JournalLobachevskii Journal of Mathematics
Volume40
Issue number11
DOIs
Publication statusPublished - 2019 Nov 1

Keywords

  • NEC SX-Aurora TSUBASA
  • Page Rank
  • SSSP
  • graph algorithms

ASJC Scopus subject areas

  • Mathematics(all)

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