Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice

Murugesan Mariappan; Yasuhiko Imai; Shigeru Kimura; Takafumi Fukushima; Ji Choel Bea; Hisashi Kino; Kang Wook Lee; Tetsu Tanaka; Mitsumasa Koyanagi

doi:10.1109/TED.2013.2295463

Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice

Murugesan Mariappan, Yasuhiko Imai, Shigeru Kimura, Takafumi Fukushima, Ji Choel Bea, Hisashi Kino, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi

Research output: Contribution to journal › Article › peer-review

4 Citations (Scopus)

Abstract

Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

Original language	English
Article number	6701183
Pages (from-to)	540-547
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	61
Issue number	2
DOIs	https://doi.org/10.1109/TED.2013.2295463
Publication status	Published - 2014 Feb

Keywords

3D-large scale integrated circuit (LSI)
Microbump
Si-lattice distortion

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice. / Mariappan, Murugesan; Imai, Yasuhiko; Kimura, Shigeru; Fukushima, Takafumi ; Bea, Ji Choel ; Kino, Hisashi; Lee, Kang Wook; Tanaka, Tetsu; Koyanagi, Mitsumasa.

In: IEEE Transactions on Electron Devices, Vol. 61, No. 2, 6701183, 02.2014, p. 540-547.

Research output: Contribution to journal › Article › peer-review

@article{931b0b59716c44fb9c67c50ba81140f6,

title = "Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice",

abstract = "Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.",

keywords = "3D-large scale integrated circuit (LSI), Microbump, Si-lattice distortion",

author = "Murugesan Mariappan and Yasuhiko Imai and Shigeru Kimura and Takafumi Fukushima and Bea, {Ji Choel} and Hisashi Kino and Lee, {Kang Wook} and Tetsu Tanaka and Mitsumasa Koyanagi",

year = "2014",

month = feb,

doi = "10.1109/TED.2013.2295463",

language = "English",

volume = "61",

pages = "540--547",

journal = "IEEE Transactions on Electron Devices",

issn = "0018-9383",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - Deteriorated device characteristics in 3D-LSI caused by distorted silicon lattice

AU - Mariappan, Murugesan

AU - Imai, Yasuhiko

AU - Kimura, Shigeru

AU - Fukushima, Takafumi

AU - Bea, Ji Choel

AU - Kino, Hisashi

AU - Lee, Kang Wook

AU - Tanaka, Tetsu

AU - Koyanagi, Mitsumasa

PY - 2014/2

Y1 - 2014/2

N2 - Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

AB - Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.

KW - 3D-large scale integrated circuit (LSI)

KW - Microbump

KW - Si-lattice distortion

UR - http://www.scopus.com/inward/record.url?scp=84893741667&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84893741667&partnerID=8YFLogxK

U2 - 10.1109/TED.2013.2295463

DO - 10.1109/TED.2013.2295463

M3 - Article

AN - SCOPUS:84893741667

VL - 61

SP - 540

EP - 547

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 2

M1 - 6701183

ER -