Abstract
Silicon-lattice distortion in the 50-μ-thick stacked large scale integrated circuit (LSI) chip over Cu-Sn μ-bumps was studied by synchrotron-assisted micro-X-ray diffraction. The top and bottom surfaces of the upper chip experienced 0.25% and 0.1% tensile strain (equivalent to 450 and 200 MPa of tensile stress), respectively. Si [004] plane showed a maximum tilt value of +0.45° and -0.25°, respectively, over the μ-bump and in the bump-space region. Raman spectroscopy revealed that upper stacked chip experienced ∼1000 MPa of tensile stress and ∼200 MPa of compressive stress, respectively, over the μ-bump and bump-space regions. Distorted Si-lattice in 3D-LSIs caused 4% and 12% change in ON-current characteristic for n- and p-MOSFET devices, respectively.
Original language | English |
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Article number | 6701183 |
Pages (from-to) | 540-547 |
Number of pages | 8 |
Journal | IEEE Transactions on Electron Devices |
Volume | 61 |
Issue number | 2 |
DOIs | |
Publication status | Published - 2014 Feb |
Keywords
- 3D-large scale integrated circuit (LSI)
- Microbump
- Si-lattice distortion
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering