Design of tamper-resistant registers for multiple-valued cryptographic processors

Yuichi Baba, Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents the design of tamper-resistant registers for multiple-valued cryptographic processors. The voltage-mode and current-mode registers are proposed for hiding dependencies between power consumption and input data. For this purpose, the voltage-mode register activates any one of two flip-flops in a complementary style, and the current-mode register maintains the number of current signals independently of the input value. This paper also applies the two registers to RSA processors in Multiple-Valued Current-Mode Logic and evaluates the power characteristics by HSIM simulations using 90nm process technology. The result shows that the proposed designs can achieve constant power consumption with lower overhead in comparison with the conventional designs.

Original languageEnglish
Title of host publicationISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic
Pages67-72
Number of pages6
DOIs
Publication statusPublished - 2010 Aug 12
Event40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 - Barcelona, Spain
Duration: 2010 May 262010 May 28

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

Other

Other40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010
CountrySpain
CityBarcelona
Period10/5/2610/5/28

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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  • Cite this

    Baba, Y., Homma, N., Miyamoto, A., & Aoki, T. (2010). Design of tamper-resistant registers for multiple-valued cryptographic processors. In ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic (pp. 67-72). [5489220] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2010.20