Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)

Seongjae Cho, Jung Hoon Lee, Shinichi O'uchi, Kazuhiko Endo, Meishoku Masahara, Byung Gook Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)
Original languageEnglish
Title of host publication2009 International Semiconductor Device Research Symposium, ISDRS '09
DOIs
Publication statusPublished - 2009 Dec 1
Externally publishedYes
Event2009 International Semiconductor Device Research Symposium, ISDRS '09 - College Park, MD, United States
Duration: 2009 Dec 92009 Dec 11

Publication series

Name2009 International Semiconductor Device Research Symposium, ISDRS '09

Other

Other2009 International Semiconductor Device Research Symposium, ISDRS '09
CountryUnited States
CityCollege Park, MD
Period09/12/909/12/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Cho, S., Lee, J. H., O'uchi, S., Endo, K., Masahara, M., & Park, B. G. (2009). Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL). In 2009 International Semiconductor Device Research Symposium, ISDRS '09 [5378143] (2009 International Semiconductor Device Research Symposium, ISDRS '09). https://doi.org/10.1109/ISDRS.2009.5378143