TY - GEN

T1 - Design of set-valued logic networks for wave-parallel computing

AU - Yuminaka, Yasushi

AU - Aoki, Takafumi

AU - Higuchi, Tatsuo

PY - 1993/1/1

Y1 - 1993/1/1

N2 - This paper presents a design of set-valued logic (SVL) networks to provide an essential solution to the interconnection problems in highly parallel VLSI systems. The basic concept is frequency multiplexing of logic values, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary functions in parallel with a single module. The systematic synthesis of wave-parallel computing system is discussed, and the possible implementation of SVL networks is addressed.

AB - This paper presents a design of set-valued logic (SVL) networks to provide an essential solution to the interconnection problems in highly parallel VLSI systems. The basic concept is frequency multiplexing of logic values, which enables us to utilize the parallelism of electrical (or optical) waves for parallel processing. This wave-parallel computing concept is capable of performing several independent binary functions in parallel with a single module. The systematic synthesis of wave-parallel computing system is discussed, and the possible implementation of SVL networks is addressed.

UR - http://www.scopus.com/inward/record.url?scp=0027252382&partnerID=8YFLogxK

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M3 - Conference contribution

AN - SCOPUS:0027252382

SN - 0818633506

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 277

EP - 282

BT - Proceedings of The International Symposium on Multiple-Valued Logic

PB - Publ by IEEE

T2 - Proceedings of the 23rd International Symposium on Multiple-Valued Logic

Y2 - 24 May 1993 through 27 May 1993

ER -