Design of robust-fault-tolerant arithmetic circuits and their application

Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

2 Citations (Scopus)

Abstract

Robust-fault-tolerant arithmetic circuits for a highly safe digital system are proposed. Two kinds of robust-fault-tolerant arithmetic circuits based on distributed coding are designed. One is a robust-fault-tolerant adder, and the other is a robust-fault-tolerant multiplier. It is shown in an experiment of robot control that the safety of the proposed arithmetic circuits is superior to that of the ordinary binary arithmetic circuits.

Original languageEnglish
Pages (from-to)2748-2751
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 1990 Dec 1
Event1990 IEEE International Symposium on Circuits and Systems Part 4 (of 4) - New Orleans, LA, USA
Duration: 1990 May 11990 May 3

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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