Design of multiple-valued linear digital circuits for highly parallel k-ary operations

Masami Nakajima, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

To design highly parallel digital circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in digital systems seems to be very attractive because analytical methods can be utilized. For unary operations, the design method of locally computable circuits have been discussed. In this paper, we propose a new design method of highly parallel multiple-valued linear digital circuits for k-ary operations using the concept of identification of input-output graphs by the introduction of multiplicated redundant symbols.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages223-230
Number of pages8
ISBN (Print)0818656522
Publication statusPublished - 1994 Jan 1
EventProceedings of the 24th International Symposium on Multiple-Valued Logic - Boston, MA, USA
Duration: 1994 May 251994 May 27

Other

OtherProceedings of the 24th International Symposium on Multiple-Valued Logic
CityBoston, MA, USA
Period94/5/2594/5/27

ASJC Scopus subject areas

  • Chemical Health and Safety
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Logic

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