Design of multiple-valued linear digital circuits for highly parallel unary operations

Masami Nakajima, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Design of locally computable combinational circuits is a very important issue in the implementation of an ultra-high-speed and compact VLSI chip. We propose a new design method for highly parallel multiple-valued linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be utilized using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. Some examples are shown to demonstrate the usefulness of the circuit design algorithm.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages283-288
Number of pages6
ISBN (Print)0818633506
Publication statusPublished - 1993 Jan 1
EventProceedings of the 23rd International Symposium on Multiple-Valued Logic - Sacramento, CA, USA
Duration: 1993 May 241993 May 27

Other

OtherProceedings of the 23rd International Symposium on Multiple-Valued Logic
CitySacramento, CA, USA
Period93/5/2493/5/27

ASJC Scopus subject areas

  • Chemical Health and Safety
  • Hardware and Architecture
  • Safety, Risk, Reliability and Quality
  • Logic

Fingerprint Dive into the research topics of 'Design of multiple-valued linear digital circuits for highly parallel unary operations'. Together they form a unique fingerprint.

Cite this