Design of multiple-valued arithmetic circuits using counter tree diagrams

Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents a novel approach to designing multiple-valued arithmetic circuits based on a unified representation of addition algorithms called Counter Tree Diagrams (CTDs). By using CTDs, we can derive possible variations of addition algorithms in a systematic way without using specific knowledge about underlying arithmetic fundamentals. For any weighted number system, we can design the optimal adder structure by trying every possible CTD representation. In this paper, the potential of the CTD-based method is demonstrated through an experimental design of the Redundant-Binary (RB) adder in multiple-valued current-mode logic. We successfully obtained the RB adder that achieves about 27-57% higher performance in terms of power-delay product compared with the conventional designs.

Original languageEnglish
Pages (from-to)487-502
Number of pages16
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume13
Issue number4-6
Publication statusPublished - 2007 Nov 29

Keywords

  • Adders
  • Arithmetic circuits
  • Circuit optimization
  • Current mode logic
  • Multiple-valued logic
  • Redundant number systems

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

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