DESIGN OF MULTIPLE-VALUED ARITHMETIC CIRCUIT BASED ON RESIDUE NUMBER SYSTEM AND ITS APPLICATION TO DIGITAL FILTER.

Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalConference articlepeer-review

1 Citation (Scopus)

Abstract

High-speed multiple-valued scaling circuits in the symmetric residue number system are studied. A new scaling algorithm based on multiple-valued logic is proposed which provides an efficient method for scaling and rounding to the closest integer on small number of levels. A hardware feasibility model for these multiple-valued residue arithmetic circuits is shown. They are multiple-input mod m//i adders and multipliers composed of linear summers, threshold detectors and T-gates which can be implemented by the technology such as ECL or I**2L. An application to a digital filter realization is also discussed, and it is shown that the high-speed 2nd-order digital filter will be constructed easily by the use of multiple-valued logic gates.

Original languageEnglish
Pages (from-to)274-280
Number of pages7
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 1979 Jan 1
EventProc Int Symp Mult Valued Logic 9th - Bath, Engl
Duration: 1979 May 291979 May 31

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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