Design of micropower CMOS quaternary memory circuits

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review


In a previous paper the authors proposed a pass transistor network composed of PMOS and NMOS transistors with different threshold voltages, which were realized by a multilevel ion‐implant technique. As a result, any quaternary logic system could be implemented. In the quaternary CMOS make‐break operator circuit, which is the basic cell of the network, the steady‐state current is essentially zero and therefore micro‐power quaternary combinational circuits can be implemented. In this paper, a micropower quaternary D‐latch circuit is designed using quaternary CMOS make‐break operator circuits. Then using the D‐latch circuit as a unit, a quaternary master‐slave flip‐flop and an up‐down T‐flip‐flop circuit are designed. Computer simulation for these circuits with SPICE‐2 confirmed their correct operation with low power dissipation. The power dissipation during the transient increases in proportion to the operating frequency. Also, a quaternary maximal‐length sequence generator is designed as an application.

Original languageEnglish
Pages (from-to)61-69
Number of pages9
JournalSystems and Computers in Japan
Issue number11
Publication statusPublished - 1987

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics


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