This paper describes a design method of high‐speed digital signal processing systems suitable for LSI fabrication. It utilizes the pulse‐train residue arithmetic circuit as a basic building block. This circuit lends itself to parallel and pipeline operations suitable f o r high‐speed digital signal processing, and permits modular‐design of the systems. A new master‐slice LSI on which the pulse‐train residue arithmetic circuits are arranged regularly, is presented. A method of minimizing the chip‐area for NMOS fabrication of the master‐slice is discussed. The layout of the pulse train residue arithmetic circuits on the LSI chip, and several parameters of the master‐slice such as the number of channels are discussed. Some demonstrative examples are presented to show the application of the master‐slice in the design of digital filter. The design method using master‐slices is relatively simple; it minimizes the chip‐count and improves the processing speed.
ASJC Scopus subject areas
- Theoretical Computer Science
- Information Systems
- Hardware and Architecture
- Computational Theory and Mathematics