Design of low‐power quaternary CMOS logic circuits

Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi

Research output: Contribution to journalArticle

Abstract

If basic quaternary logic circuits with low‐power consumption are designed in a simple way, they will be useful for high‐density VLSI implementations utilizing the feature of multivalued logic. This paper proposes a new low‐power quaternary CMOS logic circuit, which can be fabricated by a multilevel ion implant technique. The basic circuits realize functions defined by “([A‐Z]+)” and “([A‐Z]+)” operators. The circuit has two features which have not been observed so far. One is that the threshold detection of a multilevel input voltage can easily be realized by a multilevel ion implant technique. The other is that the design can be extended to any multivalued logic circuits, preserving the low‐power property, since CMOS analog switches are used for multiplexing the multivalued signals. Through the discussion of the mathematical properties of the basic operators, any combinational logic circuit can be synthesized in a very simple and systematic way. Finally, examples of the network synthesis are shown, and the operations are verified by the electronic circuit analysis program SPICE2.

Original languageEnglish
Pages (from-to)93-101
Number of pages9
JournalSystems and Computers in Japan
Volume17
Issue number3
DOIs
Publication statusPublished - 1986 Jan 1

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Information Systems
  • Hardware and Architecture
  • Computational Theory and Mathematics

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