Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama; Tsutomu Sekibe; Tatsuo Higuchi

Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod m_i multiplication can be simply performed by a shift operation. In mod m_i addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

Original language	English
Title of host publication	Proceedings of The International Symposium on Multiple-Valued Logic
Publisher	Publ by IEEE
Pages	6-13
Number of pages	8
ISBN (Print)	0818608595
Publication status	Published - 1988 Dec 1

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Cite this

Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology. / Kameyama, Michitaka; Sekibe, Tsutomu; Higuchi, Tatsuo.

Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, 1988. p. 6-13 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

@inproceedings{cceec7b239d4433db12ea85d76a603d0,

title = "Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.",

abstract = "A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.",

author = "Michitaka Kameyama and Tsutomu Sekibe and Tatsuo Higuchi",

year = "1988",

month = dec,

day = "1",

language = "English",

isbn = "0818608595",

series = "Proceedings of The International Symposium on Multiple-Valued Logic",

publisher = "Publ by IEEE",

pages = "6--13",

booktitle = "Proceedings of The International Symposium on Multiple-Valued Logic",

}

TY - GEN

T1 - Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

AU - Kameyama, Michitaka

AU - Sekibe, Tsutomu

AU - Higuchi, Tatsuo

PY - 1988/12/1

Y1 - 1988/12/1

N2 - A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

AB - A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

UR - http://www.scopus.com/inward/record.url?scp=0024140351&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0024140351&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0024140351

SN - 0818608595

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 6

EP - 13

BT - Proceedings of The International Symposium on Multiple-Valued Logic

PB - Publ by IEEE

ER -

Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Abstract

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