Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherPubl by IEEE
Pages6-13
Number of pages8
ISBN (Print)0818608595
Publication statusPublished - 1988 Dec 1

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)0195-623X

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

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