Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama; Tsutomu Sekibe; Tatsuo Higuchi

Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi

INF - Computer and Mathematical Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod m_i multiplication can be simply performed by a shift operation. In mod m_i addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

Original language	English
Title of host publication	Proceedings of The International Symposium on Multiple-Valued Logic
Publisher	Publ by IEEE
Pages	6-13
Number of pages	8
ISBN (Print)	0818608595
Publication status	Published - 1988 Dec 1

Publication series

Name	Proceedings of The International Symposium on Multiple-Valued Logic
ISSN (Print)	0195-623X

ASJC Scopus subject areas

Computer Science(all)
Mathematics(all)

Cite this

Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology. / Kameyama, Michitaka; Sekibe, Tsutomu; Higuchi, Tatsuo.

Proceedings of The International Symposium on Multiple-Valued Logic. Publ by IEEE, 1988. p. 6-13 (Proceedings of The International Symposium on Multiple-Valued Logic).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N2 - A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

AB - A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod mi multiplication can be simply performed by a shift operation. In mod mi addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10-μm CMOS technology.

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M3 - Conference contribution

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PB - Publ by IEEE

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Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology.

Abstract

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