Abstract
To realize next- generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demostrate the usefulness of the circuit design algorithm.
Original language | English |
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Pages (from-to) | 1119-1125 |
Number of pages | 7 |
Journal | IEICE Transactions on Electronics |
Volume | E76-C |
Issue number | 7 |
Publication status | Published - 1993 Jul 1 |
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering