Design of highly parallel linear digital system for ULSI processors

Masami Nakajima, Michitaka Kameyama

Research output: Contribution to journalArticlepeer-review

4 Citations (Scopus)

Abstract

To realize next- generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demostrate the usefulness of the circuit design algorithm.

Original languageEnglish
Pages (from-to)1119-1125
Number of pages7
JournalIEICE Transactions on Electronics
VolumeE76-C
Issue number7
Publication statusPublished - 1993 Jul 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Fingerprint

Dive into the research topics of 'Design of highly parallel linear digital system for ULSI processors'. Together they form a unique fingerprint.

Cite this