Design of high-radix VLSI dividers without quotient selection tables

Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

In this paper, we propose a unified high-radix division algorithm for high-speed signal and data processing applications, and present the design and evaluation of high-radix parallel dividers based on the proposed algorithm. By prescaling the input operands and converting some significant digits of a partial remainder into non-redundant representation, the quotient digit can be obtained directly from the partial remainder without using quotient digit selection tables. Performance evaluation shows that the proposed radix-4 and radix-8 divider architectures achieve faster computation with the same level of hardware complexity than the binary counterparts. We also show an experimental fabrication of a radix-4 divider chip in 0.35 μm CMOS technology.

Original languageEnglish
Pages (from-to)2623-2631
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE84-A
Issue number11
Publication statusPublished - 2001 Nov

Keywords

  • Computer arithmetic
  • High-radix division
  • SRT division
  • Signed-digit number system
  • VLSI

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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